Neurealm implemented a cost-effective OpenOCD-based debug framework over JTAG for a multi-core automotive SoC, enabling flexible and reliable debug and validation infrastructure for pre- and post-silicon activities.

Business Context

A US-based chip startup developing its first digital radar-on-chip for automotive applications needed a low-cost, customizable debug solution to accelerate software development and IP validation. Partnering with premium tools would have been too expensive, and they also wanted the framework to work on FPGA prototypes prior to final silicon.

Solutions

Neurealm recommended leveraging the open-source OpenOCD tool and architected a tailored JTAG debug framework that met custom requirements. The team engineered support for multi-core ARM architectures with AXI/AHB/APB bridges, enabling teams to validate hardware functionality, software modules, and IP blocks efficiently. This solution delivered broad customization, supported remote debugging across teams, and achieved significant cost savings compared to traditional tools.