Neurealm partnered with a world leader in networking and broadband silicon to execute the physical design of three blocks within a 3D stacked die. Operating on the 3nm TSMC node, the team took full ownership from floorplan to signoff, achieving a peak frequency of 1.5GHz and 70% utilization.

Business Context

The client required high-productivity execution for the unique complexities of 3D integrated circuit (IC) architecture. Key drivers included:
Advanced Integration: Designing a die specifically for a 3D stack environment.
Leading-Edge Process: Implementing the design on the highly complex 3nm TSMC technology node.
Design Density: Managing blocks with high utilization and a macro count of up to 50.
Turnkey Delivery: Complete ownership of the flow from netlist to GDSII.

Solutions

Neurealm implemented a comprehensive physical design flow using Innovus, Primetime, and Calibre:
3D-Specific Routing: Specialized placement and routing of Signal and Power-Ground (PG) Through-Silicon Vias (TSVs).
Custom Power Delivery: Executed custom routing to PG TSVs specifically for the One-Time Programmable (OTP) block.
Signoff & Analysis:
Performed STA signoff using Primetime.
Conducted IR and power analysis via Redhawk-SC.
Managed ECOs efficiently using Tweaker and Tempus.