Neurealm partnered with a US-based semiconductor leader to deliver a turnkey 119G SERDES test chip on a 6nm process. The project covered the full development lifecycle, from microarchitecture and design to integration, verification, DFT, and Physical Design. By managing two SERDES instances with 100K+ flip-flops, the team ensured a seamless transition from hard macro development to top-level silicon validation.

Business Context

The client required a comprehensive partner to manage the high complexity of next-generation high-speed interface testing. Key drivers included:
Turnkey Ownership: Full-lifecycle responsibility from microarchitecture to Physical Design.
Platform Adherence: Strict alignment with the customer’s specific platform requirements.
Parallel Execution: Synchronized development of the SERDES hard macro and the test chip.
Testability: Ensuring robust controllability for advanced high-speed silicon.

Solutions

Neurealm executed the design using the Cadence tool suite, focusing on integration and testability:
Advanced DFT: Implemented Hierarchical DFT (DFTM) and integrated top-level scan chains via Extest/Intest chains.
Test Control: Developed JTAG TAP controllers and TDRs for precise test-mode switching.
Pattern Porting: Successfully ported and simulated SERDES patterns at the top-level within a PE environment.
High-Density Design: Integrated two SERDES instances featuring 100K+ flip-flops and advanced scan compression.
Strategic Coordination: Maintained close alignment with customer teams to handle parallel hard macro and chip development.