Neurealm acted as a strategic partner for a world leader in networking, switching, and broadband silicon solutions to execute the physical design of 42 blocks within a VPU SoC. Utilizing the cutting-edge 3nm TSMC technology node, the team managed end-to-end ownership from floorplan to signoff. The project involved overcoming extreme density and timing hurdles to deliver production-ready results for blocks running at frequencies up to 2GHz.

Business Context

The client required a partner capable of managing massive design complexity with high resource efficiency. Key drivers included:
Advanced Technology: Implementation of designs on the highly advanced 3nm TSMC process node.
High Complexity: Navigating a workload where 100% of blocks were congestion-heavy and 90% were timing critical.
High Productivity: Achieving a model where engineers managed an average of 5 blocks, peaking at 7 blocks per engineer.
Performance Demands: Managing blocks with up to 77% utilization and a maximum macro count of 193.

Solutions

Neurealm provided complete ownership of all 42 blocks from netlist to GDSII using a specialized EDA toolchain:
Physical Design & Signoff: Employed Innovus for implementation and Primetime for STA signoff.
Power & Verification: Conducted IR and power analysis via Redhawk-SC and physical verification using Calibre.
Optimization: Utilized Tweaker and PT DMSA for efficient engineering change order (ECO) cycles.
Top-Level Closure: Leveraged Hyperscale to manage complex top-level ECO requirements.