Neurealm partnered with a US-based semiconductor company to develop a 119G SERDES test chip on TSMC 6nm. The project involved the physical implementation of four SERDES hard macro instances arranged to evaluate crosstalk effects. Neurealm owned the complete Place and Route (P&R) flow up to tape-in, navigating a heavily core-limited design with complex custom routing requirements.

Business Context

The client required a high-precision test chip to validate advanced high-speed interfaces. Key drivers included:
Turnkey Execution: Full responsibility for the P&R flow and design integration.
Advanced Node: Leveraging the TSMC 6nm technology node for 119G SERDES evaluation.
Architectural Oversight: Involvement of a senior chip architect to ensure successful execution across all design phases.
Technical Complexity: Evaluation of crosstalk through specific macro layout patterns.

Solutions

Neurealm delivered a customized physical design using Innovus, Tempus, and Calibre:
Custom Layout: Managed a core-limited design with challenging narrow channels between SERDES instances.
Precision Routing: Performed hand placement and custom routing for traces from differential clock pins to chip bumps.
Adaptive Development: Coordinated closely with the customer to handle incomplete SERDES views until very close to the tape-in deadline.
Verification & Signoff: Conducted rigorous Static Timing Analysis (STA) and Physical Verification (PV) to ensure tape-in readiness.