Neurealm partnered with a Swiss semiconductor company to provide Design for Test (DFT) for an ultra-low power connectivity sub-chip. The project involved managing a large number of analog macros and executing scan insertion, ATPG, and GLS. By deploying a specialized 4-member team, Neurealm delivered first-pass silicon success and met all test coverage targets.

Business Context

The client required expert DFT support to validate a complex mixed-signal design under ultra-low power constraints. Key drivers included:
Coverage Gap: The need to raise Stuck-At fault coverage from 80% to a target of 94%.
Macro Integration: Managing the testability of a sub-chip with a high volume of analog components.
Manufacturing Readiness: Providing ATE support and pattern delivery for test program development.

Solutions

Neurealm utilized Synopsys (DC Shell, Tetramax) and Cadence (Xcelium) to optimize the test flow:
Coverage Improvement: Achieved the 94% target through analog macro exclusions and the addition of observation points.
Advanced Testing: Successfully performed IDDQ mode at the top level and managed scan insertion.
Silicon Support: Provided critical silicon debug support to ensure design integrity post-fabrication.
Test Program Delivery: Facilitated the transition to manufacturing with comprehensive pattern delivery.