Neurealm provided independent Design for Test (DFT) execution support for a European semiconductor company’s automotive device. The team took full ownership of the DFT flow, from scan insertion to silicon debug, ensuring high reliability for the automotive and industrial markets. Through advanced ATPG and validation techniques, the project achieved first-pass silicon success with industry-leading coverage metrics.

Business Context

The client required expert, independent DFT support to meet rigorous automotive quality standards. Key drivers included:
High Coverage Targets: Achieving aggressive goals of 99.5% for Stuck-At (SA) and 93% for Transition Delay (TD).
Reliability: Ensuring first-pass silicon success through exhaustive testing and simulation.
Market Compliance: Validating the device for high-stakes automotive and industrial environments.

Solutions

Neurealm deployed a specialized 4-member team using Cadence (Genus, Xcelium) and Mentor (Tessent) tools:
Comprehensive DFT Flow: Managed scan insertion, ATPG, Gate Level Simulation (GLS), and LBIST.
Advanced Validation: Performed OCII validation, IDDQ, and VLV (Very Low Voltage) testing to maximize fault detection.
Pattern & Power Management: Utilized a WGL processor flow for IDDQ pattern merging and implemented low-power enable/disable modes.
Simulation & Debug: Conducted DMS simulations and provided direct silicon debug support to verify performance post-fabrication.