Neurealm ported an existing chipset‑level verification methodology to a Universal Verification Methodology (UVM) framework for a US‑based semiconductor customer, enabling a modern, scalable testbench architecture to support future projects.

Business Context

A semiconductor company sought a strategic partner to migrate its legacy verification infrastructure to UVM, ensuring consistent coverage and reuse across complex verification tasks. The work involved chipset‑level protocols with configurability for SER and multiple DES devices, demanding robust methodology design and integration without regressions.

Solutions

Neurealm provided UVM architecture design and ported complex testbenches and test cases from existing SystemVerilog environments into UVM. They developed simulation scripts, architected reusable verification components, integrated Cadence VIPs (I2C, SPI, I2S, DisplayPort), and ensured coverage parity with legacy methods, delivering end‑to‑end ownership of the migration.