Neurealm executed FPGA emulation of a multi‑million‑gate multimedia SoC featuring a quad‑core ARM Cortex‑A9 processor, GPU, VPU, DPU, and high‑speed peripherals, mapped across Xilinx Virtex Ultrascale FPGAs to enable early hardware/software validation.

Business Context

A Tier‑1 semiconductor customer designing a complex multimedia SoC needed an emulation platform to accelerate software development, debug hardware components, and validate high‑performance interfaces before silicon tape‑out. The workload included sophisticated video and imaging subsystems, multiple protocol interfaces, and integration of various IP blocks under constrained timing and throughput requirements to reduce risk and enhance product readiness.

Solutions

Neurealm partitioned the SoC design across multiple Xilinx Virtex Ultrascale FPGAs and integrated soft PHY for internal interfaces while using external PHYs for CSI, DSI, USB, and Ethernet. They adapted technology‑specific ASIC components for FPGA, achieved timing closure (50 + MHz for the ARM subsystem and scaled clocks for peripherals), and provided emulation debug support with software development enablement for comprehensive validation.