Neurealm partnered with a US-based company to develop a highly scalable, RISC-V compliant processor IP for high-end applications. The project focused on enhancing core units—specifically the LSU, MMU, and FPU—to support advanced multi-thread performance. A primary objective was achieving ISO 26262 certification, ensuring the design met the rigorous ASIL-D functional safety standards required for mission-critical systems.

Business Context

The client required a strategic partner to evolve their processor architecture while adhering to global safety benchmarks. Key drivers included:
Compliance: The necessity for full RISC-V compatibility and ISO 26262 alignment.
High Performance: Supporting complex in-order and out-of-order execution for high-end applications.
Safety Certification: Meeting systematic ASIL-D requirements, the highest level of automotive functional safety.
Reliability: Implementing hardware-level mechanisms to detect and mitigate potential faults.

Solutions

Neurealm provided end-to-end design and verification support using Synopsys and Cadence toolchains:
Unit Enhancement: Optimized the Load-Store (LSU), Memory Management (MMU), and Floating-Point (FPU) units for multi-thread scalability.
Execution Logic: Developed blocks to manage both in-order and out-of-order execution pathways.
Low-Level Verification: Authored test suites in RISC-V assembly language and performed detailed coverage analysis.
Functional Safety Management:
Executed fault injection and functional safety simulations.
Developed cover-points and conducted exhaustive safety simulations to ensure systematic ASIL-D compliance.