Key Responsibilities

• Develop and execute verification plans for AMS/analog IPs and mixed-signal SoCs.
• Build and maintain AMS verification environments using Verilog, Verilog-AMS, SystemVerilog, or UVM.
• Perform functional, behavioral, and mixed-signal simulations.
• Collaborate closely with analog design, digital design, and validation teams.
• Debug simulation failures and identify root causes.
• Create testbenches, assertions, coverage models, and regression suites.
• Support silicon bring-up and post-silicon validation activities when required.

Required Skills

• Strong understanding of analog and mixed-signal concepts.
• Experience with Cadence/Synopsys simulation tools.
• Knowledge of Verilog-AMS, SystemVerilog, UVM, and scripting languages like Python/Perl/Shell.
• Familiarity with ADC/DAC, PLL, SerDes, PMIC, or high-speed interface verification is preferred.
• Good debugging and problem-solving skills.

Qualification

• Bachelor’s/Master’s degree in Electronics/ECE/VLSI or related field.
• 2+ years of experience in AMS verification preferred.